The invention pertains to communications systems. More particularly, the invention pertains to the buffering of digital data transferred between a digital signal processor and subsequent processing circuitry.
In wireless communications systems such as those designed in accordance with the GSM digital cellular telephone standard utilized in Europe, most of Asia (excluding Japan), and other countries, analog data is converted into digital format and modulated on a radio frequency (RF) carrier channel for wireless transmission. At the receiving end, the signal is demodulated back to the baseband and converted back into analog form. Referring to FIG. 1 and using voice data in a digital cellular telephone as an example, in the transmit path, analog voice data from a microphone 12 is converted to digital format by an analog-to-digital converter 14 and encoded by a digital signal processor (DSP) 16. The digital data is commonly processed in a baseband circuit 18 before being forwarded to a modulation circuit 20 for frequency modulating the digital signals onto an RF carrier frequency to be output over an antenna 22.
In the receive path, RF data is received over the antenna 22, demodulated down to the baseband in demodulation circuitry 24, processed in a baseband circuit 26, and forwarded to the digital signal processor 16. The digital signal processor decodes the digital information. The decoded digital information is then converted to analog form by a digital-to-analog converter 28 and forwarded to the speaker 30 of the telephone.
In a GSM standard digital cellular telephone, the baseband chip is commonly a mixed signal chip (i.e., containing both analog and digital signals). The CSP1088 chip of the SCEPTRE chip set manufactured and sold by Lucent Technologies, Inc. of Murray Hill, N.J. is one exemplary chip designed particularly for GSM standard digital cellular telephones.
In accordance with the GSM protocol, the digital data is formatted into bursts of 148 bits. The bits are rearranged so as to spread temporally adjacent bits over a larger time frame and then reassembled at the receiving station so as to reduce the effect of lost data. A full understanding of data encoding in accordance with the GSM protocol is not necessary for an understanding of the present invention. However, the interested reader can refer to European Telecommunications Standard Institute (ETSI) Recommendation 5.03, incorporated herein by reference, for a more full explanation.
In any event, each 148 bit packet of information generated by the DSP is forwarded to the baseband processing circuitry 18 through a baseband interface circuit. The CSP1088 chip, for example, utilizes a 160 bit shift register as a transmit buffer in the aforementioned interface in the transmit data path. In particular, the DSP 16 writes data from its RAM 43 into the transmit buffer 34 and the buffer shifts the data out serially to the baseband processing circuitry 18. More particularly, the transmit buffer serially shifts out one bit at a time at the data rate of the system (e.g., 13/48 MHz for the GSM standard). When the transmit buffer is emptied of all of its data in this fashion, a TRANSMIT BUFFER EMPTY (TBE) interrupt is issued on line 38 indicating that the transmit buffer is empty. This interrupt is then serviced by the DSP which issues the address of the transmit buffer 34 on an address bus 39 and writes the next 148 bits of transmit data over data bus 40 into the transmit buffer 34 in a burst before the next bit must be read out of the buffer.
In the receive data path, a receive buffer 36 comprising two 16-bit wide, 32 location deep, registers is used to collect the demodulated received data from the baseband processing circuitry 26. Particularly, one of the registers continuously reads the incoming data until it is full. When full, a RECEIVE BUFFER FULL (RBF) interrupt signal is generated on line 42 to notify the DSP 16 that one of the registers is full. At this point, the receive buffer switches so that the incoming data stream begins filling the second register. Meanwhile, the DSP issues the address of the receive buffer 36 on address bus 39 and reads out the data from the full register over data bus 40 to the DSP""s RAM as the other register is being loaded with incoming receive data from the baseband circuitry 26. In order to prevent the overwriting of data, the DSP must finish reading the data from the first register before the second register is full.
When the second register becomes full, an interrupt is issued on line 42 notifying the DSP that the second register is full. The incoming stream of received data is then switched to begin filling the first register again while the DSP reads the data out of the second register over data bus 40.
In addition to reading the data from the receive buffer 36 and writing data to the transmit buffer 34, the DSP 16 has many other functions. These include enabling and driving the high frequency circuit section 44, including tasks such as setting frequencies and powering up the drivers as well as conditioning and formatting the transmit data before it is transferred to the transmit buffer and the receive data after it is received from the receive buffer.
In the CSP1088 chip, the transmit and receive buffers are on the same chip as the baseband processing circuitry, which is a separate chip from the chip on which the DSP 16 and RAM 43 are found. Accordingly, the data is transferred between the DSP and RAM across an external memory interface (EMI) 47 to the baseband processing circuitry chip. The EMI is not particularly relevant to the present invention and is therefore, symbolically represented by line 47 in the drawings and not discussed further herein.
The most common solution for decreasing the frequency of interrupts from the transmit and receive buffers that the DSP must service is to use very large transmit and receive buffers. Since they can hold a larger amount of data, the number of interrupts is lessened.
With the increasing number of features that are being provided on digital cellular telephones, it is expected that the processing demand on the DSP of a typical digital cellular telephone may soon outstrip its processing abilities. In particular, there is concern that the number of interrupts from various peripherals and other circuitry which must be serviced by a DSP of a digital cellular telephone may soon exceed the capabilities of present DSPs used in cellular telephones. This would lead to the need for higher powered DSPs, thus increasing cost, complexity, weight, volume and power requirements.
Accordingly, it is an object of the present invention to reduce the number of interrupts that must be serviced by a DSP in a digital cellular telephone.
In accordance with the present invention, a direct memory access (DMA) circuit is incorporated into the interface between the DSP and the baseband circuitry of a digital cellular telephone. In accordance with the present invention, interrupts indicating that the receive buffer is full or that the transmit buffer is empty are serviced by the DMA rather than the DSP, thus freeing the DSP to perform its other tasks more easily.
In accordance with a preferred embodiment of the present invention, the receive buffer and the transmit buffer are each comprised of a single, 16-bit wide, double buffered, register. An additional circuit, herein termed the translation block, is incorporated in the design to enable reading from one location (the receive buffer) and writing to a different location (the transmit buffer), as well as to arbitrate between RECEIVE BUFFER FULL (RBF) and TRANSMIT BUFFER EMPTY (TBE) interrupts, which can occur simultaneously.